The present disclosure relates generally to semiconductor devices; and more particularly, to protection of semiconductor devices from electrostatic discharge (ESD). Still more particularly, the present disclosure relates to the use of a parasitic lateral silicon controlled rectifier (SCR) ESD circuit to protect the output buffer circuit of an integrated circuit (IC) from damage caused by electrostatic discharge while preventing the output buffer circuit from a latch-up condition during normal circuit operation.
An integrated circuit (IC) contains semiconductor components (transistors) that can be damaged or destroyed by stray external electrical voltage pulses that are inadvertently discharged into the IC. It is understood that a regular supply voltage for ICs is typically 5.0, 3.3, 2.5, 1.8, 1.0 volts, or lower as specified by the IC manufacturer. Electrostatic voltages from common environmental sources can easily reach thousands, or even tens of thousands of volts. Such voltages are destructive even though the charge and any resulting current are extremely small. So, it is of critical importance to discharge any static electric charge, as it builds up, before it accumulates to a damaging voltage.
ESD protection circuitry added to the chip must allow normal operation of the IC. That means that the protection circuitry is effectively isolated from the normally operating integrated circuit core circuitry because it blocks current flow through itself to ground or any other circuit or pad. In an operating IC, electric power is supplied to a VCC pad, electric ground is supplied to a VSS pad, electronic signals are supplied from outside to internal IC pads, and electronic signals generated by the core circuitry of the IC are supplied to other internal IC pads for delivery to external circuits and devices. In an isolated, unconnected, IC all pads are considered to be electrically floating, or of indeterminant voltage. In most cases, that means that the pads are at ground, or zero, voltage.
ESD protection circuitry, therefore, has two states. In a normally operating IC, ESD protection circuitry appears invisible to the IC by blocking current through itself; and, thus, having no effect on the IC. In an isolated, unconnected IC, ESD protection circuitry serves its purpose of protecting the IC by conducting an electrostatic charge quickly to VSS ground before a damaging voltage can build up.
On-chip electrostatic discharge protection is essential in Complementary Metal-Oxide-Semiconductor (CMOS) integrated circuits. Generally, high failure threshold, small layout size, and low capacitance are required in the ESD protection circuit. As CMOS layouts are scaled down, the design of ESD protection circuits become increasingly more difficult.
It has been found that parasitic four-layer PNPN devices, also known as parasitic lateral Silicon Controlled Rectifiers (SCRs), are effective in preventing ESD damage to chips. Due to its high current sinking/sourcing capability, low turn-on impedance, low capacitance, and low power dissipation, the parasitic lateral SCR is one of the most effective devices in CMOS ESD protection. However, previous ESD circuits and methods have precluded the use of SCR in CMOS output buffer circuits due to SCR's low holding voltage (approximately 1˜2V for sub-micron devices). This low holding voltage tends to latch up the buffer circuit, thereby preventing buffer circuit from operating normally. Without additional circuitry to higher the holding voltage, the parasitic lateral SCR may not be effective in ESD protection.
Desirable in the art of integrated circuit ESD protection are additional designs utilizing SCRs with an adjustable holding voltage that provides enhanced ESD protection, thereby improving IC life and reliability.